Abstract:

This paper presents an image processing system based on smart camera platform, whose two principle elements are a Pan-Tilt-Zoom (PTZ) camera and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the PTZ Camera. With the advent of today's highly integrated Field Programmable Gate Array (FPGA) it is possible to have a software programmable processor and hardware computing resources on the same chip. Apart from having sufficient logic blocks on which the hardware is implemented these chips also have an embedded processor with system software to implement the application software around it. In this paper, the Spartan-3A DSP based Xilinx VSK platform is used for developing the proposed extensible hardware-software video streaming and processing modules. In order to develop the required hardware and software in an integrated fashion, Xilinx Embedded Development Kit (EDK) design tool has been used. A number of Xilinx provided IPs is customized to realize the hardware modules in the FPGA fabric.

Abstract:

The Fractional Motion Estimation (FME) stage enables sub-pel accuracy to be performed therefore the considered search region should be interpolated. As the half-pel and quarter-pel refinements are generally processed sequentially, the interpolation is done with two successive filtering operations. The half-pel and quarter-pel estimation differ mainly by the interpolation stage. Interpolation step is the process that consumes the most processing time of FME. Therefore, an efficient hardware accelerator for FME is indispensable. This paper presents high performance hardware architecture of Half- Pixel Motion Estimation for the H.264/AVC that targets high definition videos. It also represents new efficient interpolation architecture, which is the key to speedup half-pel refinement of all 41 Motion Vectors (MV). The result of implementation shows that a Quadruple High Definition TV videos (QHDTV- 3840x2048) in real time (30 frames/s) can be processed in real time (30 fps or faster) when the operating frequency is 300 MHz. The proposed half-pel motion estimation outperforms the well-known Yangs and Chens architectures, and achieves the refinement of all 41 sub-blocks in less than 276 clock cycles.

Abstract:

In this article we present an approach to face recognition based on the combination of feature extraction methods namely two-dimensional DWT-2DPCA and DWT-2DLDA with a neuronal network to improve system face recognition in accuracy and computation time.