|52||Securing Sensors Network Infrastructure|
The wireless sensors networks (WSN) application continues to increase with the need for an effective security mechanism. The fact that the WSN often deal with sensitive data operating in hostile environments and without monitoring, makes the concept of security considered essential. However, because of limited resources and low computing capacity of a sensor node, the development of a mechanism that ensures security is a real design challenges. In this paper, we propose two algorithms to secure the WSNs architecture: a clustering algorithm for self-organizing network and a monitoring algorithm to detect attacks.
|73||FPGA implementation of DFA Countermeasure for Embedded Systems|
To protect the Advanced Encryption Standard (AES) against side-channel attack known as Differential Fault Analysis attack, different countermeasures have been proposed. In this paper, a parity error-detection scheme has been presented in order to secure AES on 32 bits embedded system. This scheme based on parity comparison between the correct parity of the round output and the predicted parity according to the processing steps of the AES round. To evaluate the area and time costs of the proposed countermeasure, we implemented our scheme on Xilinx Virtex-5 FPGA. The experimental results show that the area overhead and the decreasing time are about 2.5% and 22% respectively. This countermeasure has high fault coverage where 93% of injected faults are detects during AES process.
|75||Security Evaluation of the AES with Countermeasure Against Multiple-Byte Fault|
Robustness of the cryptographic Advanced Encryption Standard (AES) algorithm against fault injection attacks is a great concern to ensure security. In this paper, we present a fault detection scheme, based on the information redundancy, for the Advanced Encryption Standard. We discuss the strengths and the weaknesses of this scheme against the fault injection attacks. The simulation results show that the fault coverage achieves 99.86%. Moreover, the original and the protected AES implementation have been implemented on Xilinx Virtex-5 FPGA. We proved that our implementation is very effective while keeping the area overhead very low.